DocumentCode :
1561707
Title :
Development of no-flow underfill materials and processes for Pb-free flip chip applications
Author :
Prabhakumar, Ananth ; Buckley, Donald ; Gillespie, Paul ; Mandke, Sulakshan ; Mills, Ryan ; Rubinsztajn, Slawomir ; Susarla, Prameela ; Tonapi, Sandeep
Author_Institution :
GE Global Res. Center, Niskayuna, NY
Volume :
1
fYear :
2005
Abstract :
Due to pending legislation worldwide, the semiconductor packaging industry is switching over to Pb-free electronics assembly. Flip chip packaging, which is one of the fastest growing segments of packaging technology, is also affected by this trend. It is a common practice to underfill flip chip devices to compensate for the coefficient of thermal expansion (CTE) mismatch between the die and the chip carrier. However, compatible underfill materials and processes are necessary for the effective migration of flip chip packaging towards Pb-free. Among the various underfilling techniques used in the industry, the no-flow underfill (NFU) process has the potential to increase throughput and reduce manufacturing costs as stated in D. Gamota and C. Melton (1998). There has been a significant research effort within the industry to develop NFU materials and processes for eutectic applications, but Pb-free reflow temperatures pose a significant challenge to the development of a NFU that is compatible with the Pb-free assembly process. Recently, we have developed a Pb-free compatible NFU material with a combination of self fluxing capability and cure kinetics that allows for successful assembly of 95.5Sn/3.8Ag/0.7Cu bumped flip chip devices. In this paper, the effect of various process variables that affect voiding in the underfill interface is investigated. In addition to these studies, the assembly yields for a Pb-free compatible underfill used to assemble different flip chip components with 95.5Sn/3.8Ag/0.7Cu alloy are discussed
Keywords :
assembling; copper alloys; electronics packaging; eutectic alloys; flip-chip devices; silver alloys; solders; tin alloys; voids (solid); SnAgCu; coefficient of thermal expansion mismatch; cure kinetics; flip chip packaging; lead-free electronics; no-flow underfill materials; self fluxing capability; semiconductor packaging industry; surface voiding; Assembly; Electronic packaging thermal management; Electronics industry; Flip chip; Industrial electronics; Legislation; Manufacturing industries; Semiconductor device packaging; Semiconductor materials; Thermal expansion;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Packaging Technology Conference, 2005. EPTC 2005. Proceedings of 7th
Conference_Location :
Singapore
Print_ISBN :
0-7803-9578-6
Type :
conf
DOI :
10.1109/EPTC.2005.1614420
Filename :
1614420
Link To Document :
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