DocumentCode :
1561717
Title :
Evaluating a bounded slice-line grid assignment in O(nlogn) time
Author :
Chen, Song ; Hong, Xianlong ; Dong, Sheqin ; Ma, Yuchun ; Cai, Yici ; Cheng, Chung-Kuan ; Gu, Jun
Author_Institution :
Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
Volume :
4
fYear :
2003
Abstract :
Bounded Slice-line Grid (BSG) is an elegant representation of block placement/floorplan. All block placement algorithms based on a bounded slice-line grid make use of simulated annealing or solution space smoothing where the generation and evaluation of a large number of BSG assignments is required. Therefore, a fast algorithm is needed to evaluate the BSG assignments. We present a very simple and efficient O(nlogn) algorithm to evaluate the BSG assignments. Implementation of our algorithm is significantly faster than the original O(p×q) graph-based algorithm, where p×q is BSG size. The graph-based algorithm and our algorithm are embedded in a space smoothing search procedure. Experimental results demonstrate the efficiency of our algorithm.
Keywords :
circuit layout CAD; graph theory; integrated circuit layout; network topology; simulated annealing; smoothing methods; O(nlogn) time; block floorplan; block placement algorithms; bounded slice-line grid assignment; graph-based algorithm; integrated circuit complexity; simulated annealing; solution space smoothing; space smoothing search procedure; topological representation; Computational modeling; Computer science; Costs; Integrated circuit technology; Mesh generation; Shape; Simulated annealing; Smoothing methods; Space technology; USA Councils;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN :
0-7803-7761-3
Type :
conf
DOI :
10.1109/ISCAS.2003.1206227
Filename :
1206227
Link To Document :
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