A coding method for 123 decision diagram pass transistor logic circuit synthesis

Author

Avci, M. ; Yildirim, T.

Author_Institution

Electron. & Commun. Eng. Dept., Yildiz Univ., Istanbul, Turkey

Volume

5

fYear

2003

Abstract

Pass transistor logic (PTL) circuits are known for their smaller silicon area usage, low power consumption and reduced delay advantages. The 123 decision diagram is a very effective PTL synthesis tool based on binary decisions. It realizes a logic function using NMOS pass transistors with CMOS restoring buffers. At the same time, layout of the circuit for a two metal process is obtained by this diagram. A special coding is required to apply the 123 decision diagram. Until now, the coding for the diagram has not been explained. In this paper, a very easy and effective coding method for circuit synthesis and simplification with 123 decision diagrams is proposed.

Keywords

CMOS logic circuits; binary decision diagrams; encoding; logic circuits; logic design; 123 decision diagrams; BDD; CMOS restoring buffers; NMOS pass transistors; PTL circuit coding method; binary decision diagrams; delay reduction; logic functions; pass transistor logic circuits; power consumption; silicon area usage; Boolean functions; CMOS logic circuits; Circuit synthesis; Design methodology; Logic circuits; Logic functions; MOS devices; Network synthesis; Silicon; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on

Print_ISBN

0-7803-7761-3

Type

conf

DOI

10.1109/ISCAS.2003.1206228

Filename

1206228