A hybrid floating-point/logarithmic number system digital signal processor

The implementation of a novel hybrid floating-point processor is discussed. Additions are performed without any need for exponent alignment, and multiplications and divisions are performed in less time than that required for fixed-point additions. The processor is based on a combination of the logarithmic number system (LNS) representation with the signal digit (SD) representation. The SD number system offers parallelism at the digit level for the implementation of the various operations. A novel technique for parallel conversion of SD to sign-magnitude numbers is developed to enhance the overall design. The proposed processor compares favorably to previously developed hybrid floating-point processor designs. It is at least ten gate delays faster per addition/subtraction and eight gate delays faster per multiplication/division