• DocumentCode
    1561806
  • Title

    A systematic methodology for designing area-time efficient parallel-prefix modulo 2n - 1 adders

  • Author

    Dimitrakopoulos, G. ; Vergos, H.T. ; Nikolos, D. ; Efstathiou, C.

  • Author_Institution
    Dept. of Comput. Eng. & Inf., Patras Univ., Greece
  • Volume
    5
  • fYear
    2003
  • Abstract
    In this paper a systematic methodology for designing parallel-prefix modulo 2n - 1 adders, for every n, is introduced. The resulting modulo 2n - 1 adders feature minimum logical depth and bounded fan-out loading. Additionally, an optimization technique is proposed, which aims at the reduction of redundant operators that appear on the parallel-prefix carry computation trees. Performance data reveal that the reduced structures achieve area × time complexity reduction of up to 46% when compared to previously reported designs.
  • Keywords
    adders; circuit optimisation; digital arithmetic; integrated logic circuits; logic design; area-time complexity reduction; area-time efficient adders; bounded fan-out loading; optimization technique; parallel-prefix modulo adders; redundant operators reduction; systematic design methodology; Adders; Application software; Computer networks; Concurrent computing; Design methodology; Digital arithmetic; Fault tolerant systems; High-speed networks; Informatics; Proposals;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
  • Print_ISBN
    0-7803-7761-3
  • Type

    conf

  • DOI
    10.1109/ISCAS.2003.1206237
  • Filename
    1206237
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1561806