Implementing algorithms for convolution on arrays of adders

The authors consider the problem of developing VLSI signal processors for computing convolutions. Convolutions can be efficiently computed by VLSI processors that consist of arrays of adders when they are stated in terms of matrices with elements consisting of only 1, 0, or -1. Unfortunately, when stated in matrix form the published algorithms have matrices with elements other than 1, 0, or -1. The authors explore why this occurs and show how it can be prevented when an algorithm is developed. If this fails, they propose a technique for addressing this problem that consists of replacing each such matrix by the product of two or more matrices whose elements are 1, 0, or -1