DocumentCode
1561838
Title
Noise constraint driven placement for mixed signal designs
Author
Kao, William H. ; Chu, Wen K.
Volume
4
fYear
2003
Abstract
In this paper we discuss how the problem of substrate-coupled switching noise (dI/dt and dV/dt noise) in mixed signal designs can be solved by using the substrate analysis capabilities in the SeismIC tool to drive the placement of macro cells using the Virtuoso Custom Placer (VCP) for Mixed Signal designs. An objective function consisting of area, wire length and other constraints such as substrate noise is minimized by VCP´s annealing engine and the Constraint Manager.
Keywords
circuit layout CAD; circuit optimisation; integrated circuit layout; integrated circuit modelling; integrated circuit noise; mixed analogue-digital integrated circuits; simulated annealing; Constraint Manager; SeismIC tool; VCP annealing engine; Virtuoso Custom Placer; macro cell placement; mixed signal designs; noise constraint driven placement; objective function; substrate analysis capabilities; substrate noise model; substrate-coupled switching noise; wire length; Analytical models; Circuit noise; Circuit simulation; Coupling circuits; Engines; Noise figure; Packaging; Performance analysis; Signal design; Switching circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN
0-7803-7761-3
Type
conf
DOI
10.1109/ISCAS.2003.1206241
Filename
1206241
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