DocumentCode
1561841
Title
Performance driven circuit clustering and partitioning
Author
Wang, Ling ; Selvaraj, Henry
Author_Institution
Dept. of Electr. & Comput. Eng., Nevada Univ., Las Vegas, NV, USA
fYear
2002
Firstpage
352
Lastpage
354
Abstract
In this paper, the problem of performance driven circuit partitioning is considered. The parameters taken into consideration to measure performance are power interconnection resource constraints. An algorithm is presented to build clusters in a bottom up manner while decomposing clusters for cutsize and delay minimization as well as power consumption and resource constraint. A partitioning method in a top down manner is applied based on the probability function.
Keywords
logic CAD; logic partitioning; low-power electronics; minimisation; power consumption; probability; cutsize minimization; delay minimization; performance driven circuit clustering; performance driven circuit partitioning; power consumption; power interconnection resource constraints; probability function; Circuit testing; Clustering algorithms; Delay; Energy consumption; Field programmable gate arrays; Integrated circuit interconnections; Logic circuits; Logic testing; Minimization methods; Partitioning algorithms;
fLanguage
English
Publisher
ieee
Conference_Titel
Information Technology: Coding and Computing, 2002. Proceedings. International Conference on
Print_ISBN
0-7695-1506-1
Type
conf
DOI
10.1109/ITCC.2002.1000414
Filename
1000414
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