DocumentCode
1561851
Title
A new optimization driven clustering algorithm for large circuits
Author
Ding, Cheng-Liang ; Ho, Ching-Yen ; Irwin, Mary Jane
Author_Institution
LSI Logic Corp., Milpitas, CA, USA
fYear
1993
Firstpage
28
Lastpage
32
Abstract
It is well known that doing clustering before cell placement could improve the quality of the placement and reduce the run time significantly. The authors present a clustering algorithm which is specially suitable for large designs. It uses local connectivity information to do clustering, and uses global connectivity information to do tie-breaking. Large scale real world circuits show that by this method the improvement could be up to 41% compared to the clustering method without the tie-breaker
Keywords
VLSI; integrated circuit layout; logic CAD; optimisation; VLSI; cell placement; global connectivity; local connectivity; optimization driven clustering algorithm; tie-breaking; Algorithm design and analysis; Circuits; Clustering algorithms; Computer science; Design optimization; Eigenvalues and eigenfunctions; Large scale integration; Large-scale systems; Logic; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1993, with EURO-VHDL '93. Proceedings EURO-DAC '93., European
Conference_Location
Hamburg
Print_ISBN
0-8186-4350-1
Type
conf
DOI
10.1109/EURDAC.1993.410612
Filename
410612
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