Title :
A performance driven hierarchical partitioning placement algorithm
Author :
Gao, T. ; Liu, C.L. ; Chen, K.C.
Author_Institution :
Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
Abstract :
A new hierarchical partitioning placement algorithm is presented. The objective function is formulated as a weighted sum of the total wire length and the maximum circuit delay. Special balancing rules are used to assure a good balance between the numbers of components in the regions. Total wire length and maximum circuit delay are estimated and updated efficiently at each step of the partitioning process. Experimental results are very encouraging
Keywords :
circuit layout CAD; delays; hierarchical systems; integrated circuit design; logic partitioning; optimisation; balancing rules; maximum circuit delay; objective function; performance driven hierarchical partitioning placement algorithm; total wire length; weighted sum; wire length; Algorithm design and analysis; Circuits; Computer science; Constraint optimization; Delay estimation; Partitioning algorithms; Pins; Propagation delay; Timing; Wire;
Conference_Titel :
Design Automation Conference, 1993, with EURO-VHDL '93. Proceedings EURO-DAC '93., European
Conference_Location :
Hamburg
Print_ISBN :
0-8186-4350-1
DOI :
10.1109/EURDAC.1993.410613
