Algorithms for analog VLSI 2D stack generation and block merging

In analog VLSI design, 2-axial symmetry stack and block merging are critical for mismatch minimization and parasitic control. In this paper, algorithms for analog VLSI 2-axial symmetry stack and block merging are described. We get several theory results by studying symmetric Eulerian graph and symmetric Eulerian trail. Based on those, an O(n) algorithm for dummy transistor insertion, symmetric Eulerian trail construction and 2-axial symmetry stack construction are developed. The generated stacks are 2-axial symmetric and common-centroid. Block merging algorithm is described, which is essentially independent to topological representation. Formula for calculating maximum block merging distance is given. Experimental results show effectiveness of our algorithms.