Title :
Design of MUX, XOR and D-latch SCL gates
Author :
Alioto, M. ; Palumbo, G.
Author_Institution :
Dipt. di Ingegneria dell´´Informazione, Siena Univ., Italy
Abstract :
This paper addresses the design of source-coupled logic (SCL) gates, extending previous results obtained in the simple case of an inverter. The design strategy is applied to MUX, XOR and D-latch SCL gates, and is based on a simple model of their speed and noise margin. Design equations are found to size bias current and transistors´ aspect ratio for assigned constraints on speed, power consumption and noise immunity. The expressions found are sufficiently simple for pencil-and-paper calculations and highlight the tradeoffs involved in the design. Simple design criteria are derived in typical design cases where a high speed, a low power consumption or a tradeoff are targeted. Results are validated by extensive simulations on a 0.35 μm CMOS process.
Keywords :
CMOS logic circuits; circuit simulation; flip-flops; integrated circuit design; logic design; logic gates; logic simulation; 0.35 micron; CMOS; D-latch SCL gates; MUX gates; XOR gates; bias current; design tradeoffs; noise immunity; noise margin sizing; power consumption constraint; source-coupled logic gates; speed margin; transistor aspect ratio sizing; CMOS logic circuits; CMOS technology; Circuit noise; Energy consumption; MOSFETs; Multiplexing; Optical noise; Pulse inverters; Switching circuits; Voltage;
Conference_Titel :
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN :
0-7803-7761-3
DOI :
10.1109/ISCAS.2003.1206248
