On optimizing power and crosstalk for bus coupling capacitance using genetic algorithms

The use of deep submicron (DSM) technology increases the capacitive coupling between adjacent wires leading to severe crosstalk noise, which causes power dissipation and may also lead to malfunction of the chip. In this paper, we present a technique that reduces crosstalk noise on buses based on profiling the switching behavior. Based on this profiling information, we apply an architecture that encodes pairs of bus wires, permutes the wires and assigns an inversion level to each wire in order to optimize for power and noise. The architecture configuration is obtained using a genetic algorithm. Unlike previous bus encoding approaches, crosstalk reduction can be balanced with delay and area overhead. Moreover, if delay (or area) is most critical, our architecture can be tailored to add nearly no overhead to the design. For our experiments, we used processor traces obtained from 12 SPEC2000 benchmark programs. The results show that our approach can reduce crosstalk up to 60% on address buses and up to 54% on instruction buses.