DocumentCode
1561976
Title
Analysis of output ripple in multi-phase clocked charge pumps
Author
Pylarinos, L. ; Phang, K.
Author_Institution
Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
Volume
5
fYear
2003
Abstract
This paper presents a mathematical analysis of the ripple voltage caused by a mismatch in parasitic capacitances in multi-phase, clocked charge pumps. Through detailed circuit modeling, we show that a relatively large pedestal ripple is caused by a small mismatch in parasitic capacitance. We present a simple circuit solution and verify its performance with simulation and experimental results using a 0.35 μm CMOS process.
Keywords
CMOS integrated circuits; circuit simulation; integrated circuit design; integrated circuit modelling; voltage multipliers; 0.35 micron; CMOS; charge pump output ripple; multiphase clocked charge pumps; parasitic capacitance mismatch; pedestal feedthrough; pedestal ripple; ripple voltage; voltage multiplier; CMOS technology; Capacitors; Charge pumps; Circuits; Clocks; Parasitic capacitance; Signal generators; Steady-state; Switches; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN
0-7803-7761-3
Type
conf
DOI
10.1109/ISCAS.2003.1206256
Filename
1206256
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