DocumentCode :
1562013
Title :
Development of fine pitch solders joint interconnection technology for flip chip assembly
Author :
Wei, Zhou ; Poo, Chia Yong ; Waf, Low Siu
Author_Institution :
R&D, Micron Semicond. Asia Pte Ltd., Singapore
Volume :
2
fYear :
2005
Abstract :
This paper presents the development of a new fine pitch (100 mum) solder-joint-based interconnection technology for flip chip assemblies. In contrast to existing flip chip technologies such as controlled collapse chip connection (C4) or solder alternatives like anisotropic conductive film (ACF), anisotropic conductive paste (ACP), or nonconductive paste (NCP), this method not only meets the requirements for fine pitch and high I/O density, but also provides a robust solder intermetallic (IMC) joint between die bumps and substrate bond fingers in flip chip assemblies. And perhaps even more importantly, this technology has a very low process cost. The fine pitch solder dots were pre-applied on printed circuit board (PCB) bond fingers through direct stencil printing and reflow. The stencil had apertures that were the same pitch as the die pads; thus, no redistribution layer on the die surface was necessary. Nonflow underfills were employed during flip chip assembly to bond the die on the PCB. During the die mounting process, the gold stud bump of die penetrated the oxidization layer of the solder dot. Then, when the solder dot was melted by bonder heat, it encompassed the gold bump and copper finger to form a robust intermetallic Au/Solder/Cu joint. The underfill also cured during the mounting process. Daisy chain boards with fine pitch bond fingers were constructed as a vehicle to evaluate the performance of this fine pitch interconnection technology. Both electrical tests and mechanical environment tests were performed. The initial evaluation results showed that this technology is viable in terms of its high electrical and mechanical performance and its low manufacturing cost
Keywords :
assembling; fine-pitch technology; flip-chip devices; integrated circuit interconnections; printed circuits; reflow soldering; 100 micron; Au-Cu; anisotropic conductive film; anisotropic conductive paste; bonder heat; controlled collapse chip connection; copper finger; daisy chain boards; die bumps; die mounting process; die surface; direct stencil printing; electrical tests; fine pitch solder dots; fine pitch solder joint interconnection technology; flip chip assembly; flip chip technologies; gold stud bump; mechanical environment tests; nonconductive paste; oxidization layer; printed circuit board bond fingers; redistribution layer; reflow soldering; solder alternatives; solder intermetallic joint; substrate bond fingers; Assembly; Bonding; Copper; Costs; Fingers; Flip chip; Gold; Integrated circuit interconnections; Intermetallic; Soldering;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Packaging Technology Conference, 2005. EPTC 2005. Proceedings of 7th
Conference_Location :
Singapore
Print_ISBN :
0-7803-9578-6
Type :
conf
DOI :
10.1109/EPTC.2005.1614457
Filename :
1614457
Link To Document :
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