Title :
Block digital signal processor balances performance and complexity
Author :
Khaitan, B. ; Blasco, R. ; Patel, C.N. ; Chan, K. ; Chen, S. ; Chiang, T.
Author_Institution :
Hitachi Micro Syst. Inc., San Jose, CA, USA
Abstract :
A DSP (digital signal processor) VLSI with a price/performance ratio enhanced by using properties unique to DSP is presented. The objective was to achieve much of the performance of this third-generation DSP chip at a substantially lower system cost. The device provides a 50-ns cycle time with single-level pipelining, and is packaged in a 68-pin plastic leaded chip carrier. The device is fabricated in a 1-μm CMOS process. Attention is given to the system environment, the DSP architecture, and the block sample processing
Keywords :
CMOS integrated circuits; VLSI; computerised signal processing; digital signal processing chips; pipeline processing; 1 micron; 50 ns; CMOS; DSP; Hitachi; VLSI; block sample processing; chip; digital signal processor; pipelining; plastic leaded chip carrier; Costs; Digital signal processing; Digital signal processing chips; Digital signal processors; Kernel; Packaging; Pipeline processing; Read-write memory; Signal processing; Very large scale integration;
Conference_Titel :
Acoustics, Speech, and Signal Processing, 1989. ICASSP-89., 1989 International Conference on
Conference_Location :
Glasgow
DOI :
10.1109/ICASSP.1989.266662
