An active leakage-injection scheme applied to low-voltage SRAMs

Author

De Lima, Jader A.

Author_Institution

Electr. Eng. Dept., Univ. Estadual Paulista, Guaratingueta, Brazil

Volume

5

fYear

2003

Abstract

An active leakage-injection scheme (ALIS) for low-voltage (LV) high-density (HD) SRAMs is presented. By means of a feedback loop comprising a servo-amplifier and a common-drain MOSFET, a current matching the respective bit-line leakage is injected onto the line during precharge and sensing, preventing the respective capacitances from erroneous discharges. The technique is able to handle leakages up to hundreds of μA at high operating temperatures. Since no additional timing is required, read-out operations are performed at no speed penalty. A simplified 256×1 bit array was designed in accordance with a 0.35 μm CMOS process and 1.2 V supply. A range of PSPICE simulations attests the efficacy of ALIS. With an extra power consumption of 242 μW, a 200 μA leakage @ 125°C, corresponding to 13.6 times the cell current, is compensated.

Keywords

CMOS memory circuits; SRAM chips; circuit feedback; circuit simulation; integrated circuit design; leakage currents; logic design; logic simulation; low-power electronics; 0.35 micron; 1.2 V; 125 degC; 200 muA; 242 muW; 256 bit; CMOS; active leakage-injection scheme; bit-line leakage current; cell current compensation; common-drain MOSFET; current injection; erroneous capacitance discharge; high-density SRAM; low-voltage SRAM; precharge; read-out operation speed penalty; sensing; servo-amplifier feedback loop; CMOS process; Capacitors; Circuits; High definition video; Instruments; Laboratories; Random access memory; Subthreshold current; Temperature; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on

Print_ISBN

0-7803-7761-3

Type

conf

DOI

10.1109/ISCAS.2003.1206284

Filename

1206284