• DocumentCode
    1562241
  • Title

    Signal processor SIPRO23 with minimized overhead

  • Author

    Selinger, Th ; Talmi, M.

  • Author_Institution
    Heinrich-Hertz-Inst. fur Machrichtentech., Berlin, West Germany
  • fYear
    1989
  • Firstpage
    1314
  • Abstract
    The architecture of SIPRO23 was designed with special attention to the problems of data addressing in DSP (digital signal processing) algorithms in order to achieve increased throughput. The realization of SIPRO23 with 2-μm CMOS technology requires 121 mm2 of chip area. The cycle time is estimated on the basis of simulations to be 130 ns. The derivation of the architecture and the processor components from DSP algorithms is explained
  • Keywords
    CMOS integrated circuits; digital signal processing chips; 130 ns; 2 micron; CMOS technology; DSP algorithms; SIPRO23; architecture; chip area; cycle time; data addressing; digital signal processing; processor components; signal processor; throughput; Algorithm design and analysis; Arithmetic; CMOS technology; Digital signal processing; Digital signal processing chips; Digital signal processors; Signal processing; Signal processing algorithms; Terminology; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Acoustics, Speech, and Signal Processing, 1989. ICASSP-89., 1989 International Conference on
  • Conference_Location
    Glasgow
  • ISSN
    1520-6149
  • Type

    conf

  • DOI
    10.1109/ICASSP.1989.266678
  • Filename
    266678
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1562241