An SOI 4 transistors self-refresh ultra-low-voltage memory cell

Author

Thomas, Olivier ; Amara, Amara

Author_Institution

ISEP, Paris, France

Volume

5

fYear

2003

Abstract

Analog and digital subthreshold circuit design have been investigated recently in some niche applications where performance is of secondary concern but ultra-low-power is needed. In this paper we propose a new four transistors self-refresh memory cell operating in the subthreshold region. Our simulations using a partially depleted SOI 0.25μm technology show a good stability of the cell to process and temperature variations. Combining our memory cell with a current sensing scheme and grounded bit-lines leads to good performance despite a very low supply voltage.

Keywords

CMOS memory circuits; SRAM chips; circuit simulation; circuit stability; low-power electronics; silicon-on-insulator; 0.25 micron; SOI 4 transistors self-refresh ultra-low-voltage memory cell; SOI CMOS devices; SRAM cell; analog subthreshold circuit design; current sensing scheme; digital subthreshold circuit design; grounded bit-lines; memory cell stability; partially depleted SOI 0.25 μm technology; process variations; simulations; subthreshold region; temperature variations; ultra-low power; CMOS logic circuits; CMOS technology; Circuit stability; Pacemakers; Portable computers; Random access memory; Silicon on insulator technology; Threshold voltage; Watches; Wrist;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on

Print_ISBN

0-7803-7761-3

Type

conf

DOI

10.1109/ISCAS.2003.1206296

Filename

1206296