Reducing the effect of mechanical stress on low-k die - case study

Comprehensive system-on-chip (SOC) functionality can be achieved by stacking multiple dies in a single integrated package. This is the added benefit of space efficiency and price competitiveness. Multiple dies in a single package requires the individual die to be thinned and packaged, using encapsulated mold compound (EMC), to meet overall height requirements. The cross section of a typical stacked die package was shown. As back-end-of-line (BEOL) wafer processing technology evolved from fluorinated silica glass (FSG) to low-k interlayer dielectric (ILD), this created new challenges for stacked die products. The wafer thinning process, package bill-of-material (BOM) selection, and circuit location have become critical challenges that need to be well understood. For the case study described in this paper, the low-k die was found to be sensitive to mechanical stress, which affected electrical performance. To understand the impact of package mechanical stress, mechanical simulations and impact of stress on electrical performance on sensitive analog circuits were evaluated. Multiple designs of experiments (DOEs) were carried out to better understand the cause and effect of the mechanical stresses. Finite element analysis (FEA) was performed to understand the options of reducing the mechanical stresses. The challenges included the determination of the die thickness target (via wafer backgrind process), the selections of the package assembly materials, and their effect on both FSG and low-k die