Title :
Power-delay tradeoffs in residue number system
Author :
Nannarelli, Alberto ; Cardarilli, Gian Carlo ; Re, Marco
Abstract :
In this paper we present some tradeoffs between delay and power consumption in the design of digital processors based on the Residue Number System (RNS). We focus on reducing the switching capacitance, and therefore the power, in modular adders and isomorph multipliers. Results on architectures such as FIR filters, show that the techniques used to reduce the switching capacitance not only lead to more power efficient circuits, but also to a better performance.
Keywords :
CMOS digital integrated circuits; FIR filters; adders; capacitance; delays; integrated circuit design; low-power electronics; multiplying circuits; residue number systems; FIR filters; RNS implementation; digital processor design; isomorph multipliers; modular adders; power consumption; power efficient circuits; power-delay tradeoffs; residue number system; switching capacitance; Adders; Capacitance; Clocks; Delay; Energy consumption; Finite impulse response filter; Power dissipation; Process design; Switching circuits; Voltage;
Conference_Titel :
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN :
0-7803-7761-3
DOI :
10.1109/ISCAS.2003.1206300
