DocumentCode
1562475
Title
A low power delayed-clocks generation and distribution system
Author
Kio, Su ; Chong, Kian Haur ; Sechen, Carl
Author_Institution
Dept. of Electr. Eng., Univ. of Washington, Seattle, WA, USA
Volume
5
fYear
2003
Abstract
Many new dynamic logic family techniques require a chain of delayed clocks separated by a time that is usually less than a buffer delay. This paper presents a technique to generate these clocks and distribute them to the logic gates. The system has tuning abilities so that even with process-voltage-temperature (PVT) variation in the distribution paths, it can correct itself. Extraction results for a 0.18um process showed +/- 3ps deviation from a nominal 50ps clock separation for a chain of 10 clocks at 1GHz.
Keywords
clocks; delay lock loops; logic gates; low-power electronics; 0.18 micron; 1 GHz; clock distribution system; clock generation system; delay lock loop; dynamic logic gate; low-power delayed clock; process-voltage-temperature variation; CMOS logic circuits; Clocks; Delay effects; Inverters; Jitter; Logic arrays; Logic gates; Power generation; Threshold voltage; Voltage control;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN
0-7803-7761-3
Type
conf
DOI
10.1109/ISCAS.2003.1206311
Filename
1206311
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