DocumentCode :
1562536
Title :
Design practices and issues for simultaneous switching noise
Author :
Takahashi, Narimasa ; Sato, Ken ; Honda, Yutaka
Author_Institution :
Eng. & Technol. Services, IBM Japan, Kanagawa
Volume :
2
fYear :
2005
Abstract :
This paper describes the modeling and the analysis methodology to evaluate simultaneous switching noise (SSN) for the combined system of the package with the 4-layer printed circuit board (PCB), which the 64 simultaneous switching outputs (SSOs) were included using a simple IBIS model. Simulation results showed that the ground plane in both package and PCB can be used as the reference to reduce SSN more effectively than the power plane. For the source synchronous timing technique such as used in a DDR SDRAM memory bus in the model shown in this paper, the skew control circuit technique is easy to apply in the chip design instead of using embedded capacitors in the package´s substrate. If the chip design applies both the skew control circuits for each data-signal group and slew-rate controlled output driver, SSN can keep within 5 percent of operational voltage based on the design practices and simulation results
Keywords :
integrated circuit modelling; integrated circuit noise; printed circuits; IBIS model; PCB; embedded capacitors; package substrate; printed circuit board; simultaneous switching noise; simultaneous switching outputs; skew control circuit technique; source synchronous timing technique; Capacitors; Chip scale packaging; Circuit noise; Circuit simulation; DRAM chips; Power system modeling; Printed circuits; Switching circuits; Timing; Voltage control;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Packaging Technology Conference, 2005. EPTC 2005. Proceedings of 7th
Conference_Location :
Singapore
Print_ISBN :
0-7803-9578-6
Type :
conf
DOI :
10.1109/EPTC.2005.1614512
Filename :
1614512
Link To Document :
بازگشت