Single chip stereo imager

Author

Philipp, Ray M. ; Etienne-Cummings, Ralph

Author_Institution

Dept. of Electr. & Comput. Eng., Johns Hopkins Univ., Baltimore, MD, USA

Volume

4

fYear

2003

Abstract

A stereo vision chip, incorporating two 128 × 128 pixel current-mode imagers and analog disparity computation circuitry, is presented. A modified version of block matching is used to compute the disparity between the two images at each (u, v) coordinate, with the sum-of-absolute-difference value for each possible disparity being computed in parallel. The chip has been tested at computation rates up to 11.2 million checked disparities per second, while consuming only 35 mW from a 5 V supply, including imagers and computation circuits.

Keywords

CMOS analogue integrated circuits; CMOS image sensors; analogue processing circuits; current-mode circuits; image matching; stereo image processing; 128 pixel; 16384 pixel; 35 mW; 5 V; analog computation circuitry; analog disparity computation circuitry; block matching; current-mode analog VLSI; current-mode imagers; image disparity; single chip stereo imager; standard CMOS process; stereo vision chip; sum-of-absolute-difference value; Analog computers; CMOS process; Circuit testing; Computer vision; Concurrent computing; Equations; Pixel; Registers; Stereo vision; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on

Print_ISBN

0-7803-7761-3

Type

conf

DOI

10.1109/ISCAS.2003.1206330

Filename

1206330