Title :
Tile-graph-based power planning
Author :
Fang, Jyh Perng ; Chen, Sao Jie
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
In this paper, we introduce a tile-graph-based approach to power planning. For a given floorplan solution, the power inputs are modeled into a tile graph, the minimum capacity of each power input and the maximum power need of each module in a floorplan are accumulated in an associated tile. An efficient cost evaluation algorithm is adopted to calculate the cost of power planning. As its computation time is quite short, it is reasonable to integrate such an algorithm into an iterative floorplanning environment.
Keywords :
VLSI; circuit layout CAD; graph theory; integrated circuit layout; integrated circuit packaging; iterative methods; VLSI technology; computation time; cost evaluation algorithm; flip-chip type; floorplan solution; iterative floorplanning environment; maximum power; minimum capacity; power input modeling; successive elimination algorithm; tile graph; tile-graph-based power planning; wire-bond type; Circuits; Computer architecture; Costs; Flip chip; Iterative algorithms; Power demand; Power supplies; Tiles; Voltage; Wire;
Conference_Titel :
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN :
0-7803-7761-3
DOI :
10.1109/ISCAS.2003.1206331
