Title :
Statistical modeling of gate-delay variation with consideration of intra-gate variability
Author :
Okada, Kenichi ; Yamaoka, Kento ; Onodera, Hidetoshi
Author_Institution :
Dept. of Commun. & Comput. Eng., Kyoto Univ., Japan
Abstract :
This paper proposes a model to calculate statistical gate-delay variation caused by intra-chip and inter-chip variabilities. The variation of each gate delay directly influences the variation of circuit delay, so it is important to characterize each gate-delay variation accurately. Our model characterizes the gate delay by transistor characteristics. Every transistor in a gate affects the transient characteristics of the gate, so it is indispensable to consider the intra-gate variability for the modeling of gate-delay variation. This effect is not captured in a statistical delay analysis reported so far. Our model characterizes a statistical gate-delay variation using a response surface method (RSM) and represents the intra-gate variability with a few parameters. We evaluate the accuracy of our model, and we show some simulated results of a circuit delay variation.
Keywords :
capacitance; delays; integrated circuit modelling; logic simulation; response surface methodology; RSM; circuit delay; circuit delay variation; gate-delay variation; inter-chip variabilities; intra-gate variability; response surface method; statistical modeling; transient characteristics; transistor characteristics; Circuit simulation; Computational efficiency; Delay effects; Response surface methodology; Timing;
Conference_Titel :
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN :
0-7803-7761-3
DOI :
10.1109/ISCAS.2003.1206335