DocumentCode :
1562883
Title :
An efficient tool for system-level verification of behaviors and temporal properties
Author :
Camurati, P. ; Corno, F. ; Prinetto, P.
Author_Institution :
Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
fYear :
1993
Firstpage :
124
Lastpage :
129
Abstract :
The use of process algebras is advocated as a solution for system-level description of structure, communication, and behavior, while an action-based temporal logic is used to specify and check system-level properties. It is shown how SEVERO, a tool for describing and verifying finite state systems, can be used to integrate in the unified framework of symbolic manipulations both descriptive and prescriptive aspects. Experimental results show the efficiency of the BDD (binary decision diagram)-based implementation of the proof procedures
Keywords :
finite state machines; formal verification; logic CAD; logic design; process algebra; symbol manipulation; temporal logic; SEVERO; action-based temporal logic; behaviors; binary decision diagram; equivalence; finite state systems; process algebras; symbolic manipulations; system-level description; system-level verification; temporal properties; Algebra; Automatic logic units; Boolean functions; Data structures; Hardware; Logic functions; Microprogramming; Software testing; Speckle; System testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 1993, with EURO-VHDL '93. Proceedings EURO-DAC '93., European
Conference_Location :
Hamburg
Print_ISBN :
0-8186-4350-1
Type :
conf
DOI :
10.1109/EURDAC.1993.410626
Filename :
410626
Link To Document :
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