DocumentCode
1563170
Title
Control signal sharing of asynchronous circuits using datapath delay information
Author
Saito, Hiroshi ; Kim, Euiseok ; Imai, Masashi ; Sretasereekul, Nattha ; Nakamura, Hiroshi ; Nanya, Takashi
Author_Institution
RCAST, Univ. of Tokyo, Japan
Volume
5
fYear
2003
Abstract
Due to state explosion problem in synthesis, most of asynchronous CAD tools based on graph models cannot handle large specifications. To overcome this problem, in this paper, we propose two control signal sharing methods by using the delay information of datapath circuits. The reductions of signals by sharing reduce the number of states significantly and result in area optimal circuits. They are carried out at control flow graph (CFG) descriptions in terms of node sharing. Experimental results are encouraging in that a number of control signals are shared.
Keywords
asynchronous circuits; data flow graphs; delays; logic CAD; CAD tool; asynchronous circuit; control flow graph; control signal sharing; datapath delay; graph model; logic synthesis; node sharing; state explosion; Asynchronous circuits; Circuit synthesis; Delay; Explosions; Flow graphs; Level control; Libraries; Logic circuits; Registers; Signal synthesis;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN
0-7803-7761-3
Type
conf
DOI
10.1109/ISCAS.2003.1206388
Filename
1206388
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