Hardware Architecture of MAP Algorithm for Turbo Codes Implemented in a FPGA

Turbo codes represent a very powerful channel coding technique for next generation of mobile communications. In our days, the research is focus on the development and implementation of turbo coding-decoding algorithms in high-speed programmable platforms (DSP’s and FPGA’s) for a better performance in terms of error correction, power consumption and speed. MAP (Maximum A-posteriori probability) algorithm represents the best performance choice for turbo decoding block. The main objective of implementation is to design structures for turbo decoding near to the theoretical performances using sub-optimal architectures. In this work we present a hardware implementation of the Log-domain version of the MAP algorithm (Log-MAP). This version of the algorithm gives an excellent approach to the Shannon limits and allows the description of simple blocks based on arithmetic operators, like MAX* operator.