• DocumentCode
    1564049
  • Title

    Architectural support for arithmetic in optimal extension fields

  • Author

    Groszschaedl, J. ; Kumar, Sandeep S. ; Paar, Christof

  • Author_Institution
    IAIK, Graz Univ. of Technol., Austria
  • fYear
    2004
  • Firstpage
    111
  • Lastpage
    124
  • Abstract
    Public-key cryptosystems generally involve computation-intensive arithmetic operations, making them impractical for software implementation on constrained devices such as smart cards. We investigate the potential of architectural enhancements and instruction set extensions for low-level arithmetic used in public-key cryptography, most notably multiplication in finite fields of large order. The focus of the present work is directed towards a special type of finite fields, the so-called optimal extension fields GF(pm) where p is a pseudo-Mersenne (PM) prime of the form p = 2n - c that fits into a single register. Based on the M/PS32 instruction set architecture, we introduce two custom instructions to accelerate the reduction modulo a PM prime. Moreover, we show that the multiplication in an optimal extension field can take advantage of a multiply/accumulate unit with a wide accumulator so that a certain number of 64-bit products can be summed up without overflow. The proposed extensions support a wide range of PM primes and allow a reduction modulo 2n - c to complete in only four clock cycles when n ≤ 32.
  • Keywords
    digital arithmetic; instruction sets; number theory; public key cryptography; M/PS32 instruction set architecture; architectural support; computation-intensive arithmetic operations; instruction set extensions; low-level arithmetic; optimal extension fields; pseudoMersenne prime; public-key cryptosystems; Acceleration; Arithmetic; Clocks; Computer architecture; Elliptic curve cryptography; Elliptic curves; Galois fields; Public key cryptography; Security; Smart cards;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Application-Specific Systems, Architectures and Processors, 2004. Proceedings. 15th IEEE International Conference on
  • ISSN
    2160-0511
  • Print_ISBN
    0-7695-2226-2
  • Type

    conf

  • DOI
    10.1109/ASAP.2004.1342463
  • Filename
    1342463