DocumentCode :
1564075
Title :
Binary multiplication based on single electron tunneling
Author :
Lageweg, Casper ; Cotofana, Sorin ; Vassiliadis, Stamatis
Author_Institution :
Dept. of Microelectron. & Comput. Eng., Delft Univ. of Technol., Netherlands
fYear :
2004
Firstpage :
152
Lastpage :
166
Abstract :
This work investigates single electron tunneling based implementations of 16 and 32-bit tree multipliers operating according to the single electron encoded logic paradigm. First, we propose implementations for a set of basic components (13/2 counter, 7/3 counter) and verify them by means of simulation. Second, we propose 16 and 32-bit tree multipliers based on these components, and analyze these multipliers in terms of area, delay and power consumption. Third, we investigate alternative designs for the 32-bit multiplier and conclude that the 7/3 counter based implementations are less effective than expected. We consequently propose improved 7/3 counters and evaluate the implications of these new designs on the area, delay and power consumption of the 16 and 32-bit multipliers.
Keywords :
delays; digital arithmetic; logic gates; nanotechnology; single electron devices; tunnelling; 16 bit tree multipliers; 32-bit tree multipliers; binary multiplication; single electron encoded logic; single electron tunneling; Costs; Counting circuits; Delay; Electrons; Energy consumption; Logic gates; Temperature; Tunneling; Virtual colonoscopy; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Application-Specific Systems, Architectures and Processors, 2004. Proceedings. 15th IEEE International Conference on
ISSN :
2160-0511
Print_ISBN :
0-7695-2226-2
Type :
conf
DOI :
10.1109/ASAP.2004.1342466
Filename :
1342466
Link To Document :
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