Conditional and unconditional hardware sharing in pipeline synthesis

This paper addresses the following problem: given a set of functional units and a data introduction interval, find a pipelined schedule for the given behavioral description (which may contain conditionals) that minimizes the number of pipeline stages. The approach taken to solve this problem is to do conditional and unconditional hardware sharing simultaneously while scheduling. A two-phase algorithm is used. The first phase tries to find a feasible solution (if it exists), while the second phase improves the initial solution by reducing the number of pipeline stages and the number of pipeline registers. The fast heuristics used to do this have been found to give excellent results