Architectural tradeoffs in synthesis of pipelined controls

Current synthesis approaches do not take into account the impact of the underlying architecture during operations like scheduling and binding. This results in synthesis algorithms that can produce designs only for a single architecture. The design space that can be explored by such a synthesis tool is limited. The authors examine three architectures that have different control pipelining strategies. They derive the important constraints that these architectures impose on the scheduling algorithm and propose an algorithm that incorporates these constraints when producing a schedule. They also demonstrate through several experiments that by being able to synthesize for a given control pipeline architecture, they can provide designers with a wide range of area-delay tradeoffs