Title :
A method for diagnosing implementation errors in synchronous sequential circuits and its implications on synthesis
Author :
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution :
Dept. of Electr. & Comput. Eng, Iowa Univ., Iowa City, IA, USA
Abstract :
The authors consider the problem of diagnosing implementation errors in synchronous sequential circuits described by state tables. The diagnosis problem is formulated so as to provide the erroneously implemented entries of the state table, which are useful for the purposes of debugging the synthesis procedure. The diagnosis procedure developed is not limited to a specific error model and no bound is set on error multiplicity. Experimental results are presented to show the effectiveness of this procedure. The experiments indicate that state tables with certain properties make their implementations more amenable to diagnosis than others. These properties are used as guidelines for synthesis
Keywords :
design for testability; fault diagnosis; logic CAD; logic design; logic testing; sequential circuits; debugging; effectiveness; error model; error multiplicity; implementation errors; state tables.; synchronous sequential circuits; synthesis; Circuit synthesis; Cities and towns; Computer errors; Debugging; Guidelines; Process design; Sequential circuits;
Conference_Titel :
Design Automation Conference, 1993, with EURO-VHDL '93. Proceedings EURO-DAC '93., European
Conference_Location :
Hamburg
Print_ISBN :
0-8186-4350-1
DOI :
10.1109/EURDAC.1993.410646
