Title :
90nm Games Processor Wafer to Module Power Yield Optimization
Author :
Mallette, Raymond ; Rawlins, Brad
Author_Institution :
IBM Microelectron., Essex Junction, VT
Abstract :
When fabricating a high volume games processor (CPU) for the consumer market, due to the cost of the module package, it is important to optimize the functional yield loss between the wafer die and the finished module package. For a performance CPU in a mature 90 nm technology the primary yield drivers can be power and performance. A functional power Iddq screen test method is presented here that decreases yield loss across functional test sectors by minimizing the impact of process variation for device gate leakage.
Keywords :
microprocessor chips; wafer level packaging; device gate leakage; functional power screen test; functional yield loss; games processor wafer; module package; module power yield optimization; size 90 nm; wafer die; CMOS process; CMOS technology; Cost function; Current measurement; Gate leakage; Microelectronics; Packaging; Performance loss; Power measurement; Semiconductor device testing; CMOS Device Gate Leakage; CMOS Device Process Variability; Iddq Screening; Wafer to Module Test Yield Optimization;
Conference_Titel :
Advanced Semiconductor Manufacturing Conference, 2008. ASMC 2008. IEEE/SEMI
Conference_Location :
Cambridge, MA
Print_ISBN :
978-1-4244-1964-7
Electronic_ISBN :
1078-8743
DOI :
10.1109/ASMC.2008.4529050
