• DocumentCode
    1564717
  • Title

    A quality-cost model of in-line inspections for excursion detection and reduction

  • Author

    Hall, Gavin D R ; Young, Roger ; Dunne, Matt ; Muro, Mina

  • Author_Institution
    Defect & Device Yield Eng., ON Semicond., Gresham, OR
  • fYear
    2008
  • Firstpage
    273
  • Lastpage
    277
  • Abstract
    A methodology for optimized defect excursion (EXR) monitoring is proposed using an economic statistical process control (SPC) model for defect limited yield. The cost of in-line defect inspections is increasing at an exponential rate, particularly for a 300 mm fabrication facility. Therefore, optimized in-line inspection schemes have become more critical for controlling the costs of semiconductor manufacturing. In order to minimize the inspection costs while maintaining acceptable yield, a cost function which incorporates the power of the inspection, the interval between inspections, and the yield impact (cost) is optimized for all inspection locations in a given process flow with a fixed sampling budget. This methodology can be used to allocate inspections based upon the risk of yield excursions at defect limited process layers. This model can also be used to establish quantitative estimates of return on investment (ROI) of inspections to inform decisions regarding purchase of in-line monitoring (ILM) tools or sampling adjustment. A quality-cost model has been derived using the theory of economic SPC, and has been implemented in a high volume CMOS fabrication facility with a high degree of success.
  • Keywords
    electron device manufacture; inspection; process monitoring; statistical process control; defect limited yield; economic statistical process control model; excursion detection; excursion reduction; in-line inspections; in-line monitoring; optimized defect excursion monitoring; quality cost model; semiconductor manufacturing; Cost function; Fabrication; Inspection; Monitoring; Optimization methods; Power generation economics; Process control; Sampling methods; Semiconductor device manufacture; Semiconductor device modeling; Advanced SPC techniques; Cost Reduction; Cost of Ownership; Defect Inspection; Defect-to-Yield correlation; Yield Enhancement;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Advanced Semiconductor Manufacturing Conference, 2008. ASMC 2008. IEEE/SEMI
  • Conference_Location
    Cambridge, MA
  • ISSN
    1078-8743
  • Print_ISBN
    978-1-4244-1964-7
  • Electronic_ISBN
    1078-8743
  • Type

    conf

  • DOI
    10.1109/ASMC.2008.4529052
  • Filename
    4529052