DocumentCode :
1564762
Title :
FPGA Implementation of Infomax BSS Algorithm with Fixed-Point Number Representation
Author :
Li, Zhongfeng ; Lin, Qiuhua
Author_Institution :
Sch. of Electron. & Inf. Eng., Dalian Univ. of Technol.
Volume :
2
fYear :
2005
Firstpage :
889
Lastpage :
892
Abstract :
Blind source separation (BSS) has promising applications in many fields such as communications and biomedical engineering. It is often necessary to realize the BSS algorithm in real time. In this paper field programmable gate arrays (FPGA) is used to implement the information-maximization (Infomax) algorithm of BSS with a fixed-point number representation. A system design of the Infomax BSS algorithm in the case of 2 inputs and 2 outputs is presented by using the Quartus II, the DSP builder and the Simulink. Compared with ASIC design, FPGA implementation has many advantages including short development time, convenient design platforms and low costs
Keywords :
application specific integrated circuits; blind source separation; field programmable gate arrays; logic design; random number generation; ASIC design; FPGA implementation; blind source separation; field programmable gate arrays; fixed-point number representation; infomax BSS algorithm; information-maximization; Algorithm design and analysis; Application specific integrated circuits; Biomedical engineering; Blind source separation; Field programmable gate arrays; Hardware; Independent component analysis; Sonar detection; Source separation; Speech analysis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Neural Networks and Brain, 2005. ICNN&B '05. International Conference on
Conference_Location :
Beijing
Print_ISBN :
0-7803-9422-4
Type :
conf
DOI :
10.1109/ICNNB.2005.1614764
Filename :
1614764
Link To Document :
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