Title :
The energy impact of aggressive loop fusion
Author :
Zhu, YongKang ; Magklis, Grigorios ; Scott, Michael L. ; Ding, Chen ; Albonesi, David H.
Author_Institution :
Dept. of Electr. & Comput. Eng., Rochester Univ., NY, USA
Abstract :
Loop fusion combines corresponding iterations of different loops, ft is traditionally used to decrease program run time, by reducing loop overhead and increasing data locality. In this paper, however, we consider its effect on energy. By merging program phases, fusion tends to increase the uniformity, or balance of demand for system resources. On a conventional superscalar processor, increased balance tends to increase IPC, and thus dynamic power, so that fusion-induced improvements in program energy are slightly smaller than improvements in program run time. If IPC is held constant, however, by reducing frequency and voltage - particularly on a processor with multiple clock domains - then energy improvements may significantly exceed run time improvements. We demonstrate the benefits of increased program balance under a theoretical model of processor energy consumption. We then evaluate the benefits of fusion empirically on synthetic and real-world benchmarks, using our existing loop-fusing compiler and a heavily modified version of the SimpleScalar/Wattch simulator. For the real-world benchmarks, we demonstrate energy savings ranging from 7-40%, with run times ranging from 1% slowdown to 17% speedup. In addition to validating our theoretical model, the simulation results allow us to "tease apart" the factors that contribute to fusion-induced time and energy savings.
Keywords :
instruction sets; optimising compilers; parallel processing; power consumption; program control structures; resource allocation; IPC; SimpleScalar/Wattch simulator; clock domains; fusion-induced energy savings; fusion-induced time savings; loop overhead; loop-fusing compiler; processor energy consumption; program run time; superscalar processor; system resource demand balance; Clocks; Computer science; Dynamic voltage scaling; Energy consumption; Energy efficiency; Frequency; Merging; Optimizing compilers; Program processors; Voltage control;
Conference_Titel :
Parallel Architecture and Compilation Techniques, 2004. PACT 2004. Proceedings. 13th International Conference on
Print_ISBN :
0-7695-2229-7
DOI :
10.1109/PACT.2004.1342550