DocumentCode
1564912
Title
RNS approach to fast dividers
Author
Cadarilli, G.C. ; Lojacono, R. ; Salerno, M.
Author_Institution
Dept. of Electron. Eng., Rome Univ., Italy
fYear
1989
Firstpage
2389
Abstract
The authors propose a residue number system (RNS) architecture that realizes fast division. This architecture is fully developed in the particular case of eight-bit wordlength; in this case significant simplifications are reached. The whole divider appears as a combinatorial structure. A layout of the proposed architecture has been realized in a 1.5-μm CMOS technology, SPICE simulation of the circuit extracted from this layout has shown the overall propagation time in performing the division to be about 100 ns
Keywords
CMOS integrated circuits; computerised signal processing; digital signal processing chips; 1.5 micron; 100 ns; CMOS technology; DSP chips; RNS; SPICE simulation; architecture; combinatorial structure; digital signal processing; fast dividers; propagation time; residue number system; Adders; Arithmetic; CMOS technology; Circuit simulation; Digital signal processing; Iterative algorithms; Iterative methods; SPICE; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Acoustics, Speech, and Signal Processing, 1989. ICASSP-89., 1989 International Conference on
Conference_Location
Glasgow
ISSN
1520-6149
Type
conf
DOI
10.1109/ICASSP.1989.266948
Filename
266948
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