A high speed fixed point binary divider

The use of recently developed pass transistor design techniques permits the design of an extremely regular, ultrasmall, but flexible high speed fixed point binary divider. This architecture allows a division module to be part of a general purpose DSP processor, just as multipliers are today. Special-purpose divider ships with very high data rates can also be created with this architecture. The circuit is small enough that many dividers, operating as pipelines, as parallel circuits, or as pipelined/parallel combinations, can be integrated on a single die. A chip containing twenty-four 16-bit dividers has been designed and fabricated. The dividers operate in parallel at a worst case clock rate of 20 MHz. This chip contains 152786 transistors and is 6.4 mm by 6.6 mm, yielding an overall chip density of 276 μm² per device, including the pads