A reconfigurable fault-tolerant signal processor

Describes a parallel computer architecture targeted at signal pattern analysis applications, scalable to configurations capable of TeraFLOP (10¹² floating point operations per second) throughput. An important attribute of the architecture is its low interconnection overhead, making it well suited to miniaturization using advanced packaging. Preliminary design and thermal tests project a computing density of 300 GigaFLOPS per cubit foot. The architecture is reconfigurable as a tree machine, one or more rings, or a set of linear systolic arrays. Fault tolerance is achieved by embedding these topologies within a four-connected lattice, growing around any faults. A performance model is derived and used to analyze the impact of skewness of the embedded trees on the execution time of parallel recognition algorithms