Neural Network Macromodel for High-Level Power Estimation of CMOS Circuits

A novel power macromodeling technique was developed for high-level power estimation of complementary metal-oxide-semiconductor (CMOS) circuits based on backpropagation neural network (BPNN). The dependence of power dissipation on a circuit´s primary input/output statistics was captured to construct the power macromodel by extracting certain features from the input/output streams. In contrast to previous modeling techniques, it does not require empirically construct specialized analytical equations, and achieves better accuracy by taking into account the statistics of not only the primary inputs, but also the primary outputs. It could yield power estimates within seconds, because it does not perform any simulation during estimation. In experiments with the ISCAS-85 circuits, the average absolute relative error of the macromodel was below 5.0% for most of the circuits. The root-mean-square (RMS) error is about 1 - 2%. In addition to power dissipation, statistics of a circuit´s primary outputs could be simultaneously obtained as a by-product, which is very useful for power estimation of core-based systems-on-chip (SoCs) with pre-designed blocks