Very high efficiency VLSI chip-pair for full search block matching with fractional precision

VLSI architecture design and implementation of a chip pair for the motion compensation full search block matching algorithm are described. This pair of ASICs (application-specific integrated circuits) is motivated by the intensive computational demands for performing motion compensation in real time. They have been developed to calculate fractional motion vectors with quarter-pel precision. The VLSI architecture is based on some special data-flow designs that allow sequential inputs but perform parallel processing with 100% efficiency for integer motion vector estimation and nearly 100% for fractional motion vector estimation. The chip-pair design has been laid out and simulated using a silicon compiler tool, and the chip statistics are summarized. Testing circuitry is included to increase the observability of the chips