DocumentCode
1565183
Title
A CMOS implementation of a variable step size digital adaptive filter
Author
Evans, Joseph B. ; Liu, Bede
Author_Institution
Dept. of Electr. Eng., Princeton Univ., NJ, USA
fYear
1989
Firstpage
2489
Abstract
The authors consider the implementation of the combined variable-step-size (VS)-power-of-two quantizer-multiplier (PTQ) algorithm in a 2.5-μm CMOS process. A 7-MHz chip with four taps, using dedicated hardware for each tap, and a 32-kHz chip with 63 taps, using multiplexed processing hardware, are presented. The area and speed performance figures for these chips are comparable with recently published results when λ-rule scaling is used; however, the performance of the VS-PTQ algorithm is superior
Keywords
CMOS integrated circuits; adaptive filters; digital filters; 2.5 micron; 32 kHz; 7 MHz; CMOS process; HF; LF; area; multiplexed processing hardware; power of two quantizer multiplier; speed performance; variable step size digital adaptive filter; Adaptive algorithm; Adaptive filters; Algorithm design and analysis; Arithmetic; CMOS process; Convergence; Counting circuits; Hardware; Least squares approximation; Steady-state;
fLanguage
English
Publisher
ieee
Conference_Titel
Acoustics, Speech, and Signal Processing, 1989. ICASSP-89., 1989 International Conference on
Conference_Location
Glasgow
ISSN
1520-6149
Type
conf
DOI
10.1109/ICASSP.1989.266972
Filename
266972
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