DocumentCode
156539
Title
Output selection for test response compaction based on multiple counters
Author
Wei-Cheng Lien ; Kuen-Jong Lee ; Chakrabarty, Krishnendu ; Tong-Yu Hsieh
Author_Institution
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
fYear
2014
fDate
28-30 April 2014
Firstpage
1
Lastpage
4
Abstract
Recently a novel test response compaction method called output selection is proposed to achieve high compaction ratio and high diagnosibility by observing only a subset of output response bits. In addition, this method also ensures zero aliasing and no unknown-value problem. Previously, a single counter and a multiplexer are employed as selection logic for output selection on scan-based designs. This single-counter-based approach may need to apply one pattern several times in order to observe all selection responses, hence may significantly increase the test application time. To address this weakness, this paper presents a multiple-counter-based output selection method to observe more than one output response bits at each scan-out cycle. A new response selection algorithm is developed to determine desired responses under a set of pre-defined counter operations. Results on IWLS´05 benchmarks show that compared with the single counter-based scheme, the proposed method can reduce 47.33%~67.87% test application time with only slight increase on area overhead.
Keywords
counting circuits; logic design; logic testing; multiplexing equipment; IWLS´05 benchmarks; multiple counters; multiple-counter-based output selection method; multiplexer; response selection algorithm; scan-based designs; single counter-based scheme; test response compaction; Algorithm design and analysis; Benchmark testing; Circuit faults; Compaction; Fault detection; Multiplexing; Radiation detectors;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, Automation and Test (VLSI-DAT), 2014 International Symposium on
Conference_Location
Hsinchu
Type
conf
DOI
10.1109/VLSI-DAT.2014.6834865
Filename
6834865
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