An efficient systolic array VLSI cell architecture for the implementation of transversal filter based on the quadratic residue number systems

The author presents efficient direct and indirect implementations of transversal filter architectures using the quadratic residue number system (QRNS). In the case of the direct transversal filter, a systolic array architecture has been developed using very efficient computational cells. In the case of a transform domain implementation, a pipelined architecture is proposed in which single multiplexed ROMs are used as computational cells to reduce the number of ROMs in the design