A new logic minimization method for multiplexor-based FPGA synthesis

A new method was presented for the minimization of incompletely specified functions using MBDs (modified binary decision diagrams: ROBDDs with a don´t care terminal). The cost function to be minimized is the MBD size, which is an important factor in the case of FPGA synthesis. The method developed is based on a subgraph matching target to reduce the number of nodes of a MBD. The matching relies on the presence of a third terminal value X (don´t care) in the MBD in order to represent an incompletely specified function in a single graph. The authors have compared the new method with ESPRESSO with respect to MBD size reduction and multiplexor based synthesis. The results obtained empirically confirm the initial hypothesis that two-level minimization techniques are inadequate for this purpose, and also show the efficiency of the proposed algorithm