DocumentCode :
156554
Title :
Full system simulation framework for integrated CPU/GPU architecture
Author :
Po-Han Wang ; Gen-Hong Liu ; Jen-Chieh Yeh ; Tse-Min Chen ; Hsu-Yao Huang ; Chia-Lin Yang ; Shih-Lien Liu ; Greensky, James
Author_Institution :
Dept. of Comput. Sci. & Inf. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fYear :
2014
fDate :
28-30 April 2014
Firstpage :
1
Lastpage :
4
Abstract :
The integrated CPU/GPU architecture brings performance advantage since the communication cost between the CPU and GPU is reduced, and also imposes new challenges in processor architecture design, especially in the management of shared memory resources, e.g, the last-level cache and memory bandwidth. Therefore, a micro-architecture level simulator is essential to facilitate researches in this direction. In this paper, we develop the first cycle-level full-system simulation framework for CPU-GPU integration with detailed memory models. With the simulation framework, we analyze the communication cost between the CPU and GPU for GPU workloads, and perform memory system characterization running both applications concurrently.
Keywords :
cache storage; graphics processing units; logic design; microprocessor chips; shared memory systems; full system simulation framework; integrated CPU-GPU architecture; last-level cache; memory bandwidth; memory system characterization; micro-architecture level simulator; processor architecture design; shared memory resources; Bandwidth; Graphics processing units; Kernel; Memory management; Synchronization;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, Automation and Test (VLSI-DAT), 2014 International Symposium on
Conference_Location :
Hsinchu
Type :
conf
DOI :
10.1109/VLSI-DAT.2014.6834872
Filename :
6834872
Link To Document :
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