DocumentCode :
156558
Title :
A power delivery network (PDN) engineering change order (ECO) approach for repairing IR-drop failures after the routing stage
Author :
Tsu-Wei Tseng ; Chang-Tzu Lin ; Chia-Hsin Lee ; Yung-Fa Chou ; Ding-Ming Kwai
Author_Institution :
Inf. & Commun. Res. Labs., Ind. Technol. Res. Inst., Hsinchu, Taiwan
fYear :
2014
fDate :
28-30 April 2014
Firstpage :
1
Lastpage :
4
Abstract :
PDN evaluation/synthesis techniques have been used to facilitate the planning/construction of PDNs in integrated circuits at early physical implementation stages. They are rarely relevant after the routing stage when few routing resources are left and hence call for a repair strategy. The reason is that the traditional methods often apply wire widening or wire density increment directly without taking signal routing into account. Moreover, intuitively adding connections to the PDNs using the entire space available is quite time-consuming and eventually leads to lack of routing resources for later design ECO. Therefore, in this paper, we propose an approach to efficiently repairing the PDNs at the signoff stage. The greedy-Pareto-optimal (GPO) method is used to select the most effective regions to enhance the power rail connectivity. Maximizing the IR-drop improvement and minimizing the use of routing resources are considered at the same time. The method has been incorporated in our backend design flow and verified by leveraging a commercial P&R tool. On a test case of image signal processor, the experimental results show that the proposed PDN ECO approach can improve the worst IR-drop from 9.34% to 3.84% (i.e., 58.9% improvement) in the post-routing stage, where the ECO wire pitch is 3.5 times the minimal routing pitch.
Keywords :
Pareto optimisation; integrated circuit design; network routing; power integrated circuits; ECO wire pitch; GPO method; IR-drop failures; IR-drop improvement; PDN ECO approach; PDN evaluation techniques; PDN synthesis techniques; engineering change order approach; greedy-Pareto-optimal method; image signal processor; integrated circuits; post-routing stage; power delivery network; power rail connectivity; routing resources; wire density; wire widening; Integrated circuits; Metals; Planning; Rails; Routing; Runtime; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, Automation and Test (VLSI-DAT), 2014 International Symposium on
Conference_Location :
Hsinchu
Type :
conf
DOI :
10.1109/VLSI-DAT.2014.6834874
Filename :
6834874
Link To Document :
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