Title :
Technology mapping for sequential circuits based on retiming techniques
Author :
Weinmann, Ulrich ; Rosenstiel, Wolfgang
Author_Institution :
Comput. Sci. Res. Center, Karlsruhe Univ., Germany
Abstract :
A new technology mapping technique for implementing sequential circuits by table lookup FPGAs (field programmable gate arrays) with predefined memory elements is presented. Most mapping algorithms in this field are restricted to combinational logic. The presented methods for optimizing delay and area consumption are based on a redesign of the circuit with retiming and specific sequential transformations. Experimental results of several benchmark circuits show an improvement of up to 20% less area consumption and delay in comparison to existing tools
Keywords :
delays; field programmable gate arrays; logic CAD; logic design; optimisation; performance evaluation; programmable logic arrays; sequential circuits; table lookup; Xilinx 3000 architecture; area consumption; benchmark circuits; delay; field programmable gate arrays; mapping algorithms; predefined memory elements; retiming; sequential circuits; sequential transformations; table lookup FPGAs; Clocks; Combinational circuits; Computer science; Delay; Field programmable gate arrays; Logic circuits; Optimization methods; Registers; Sequential circuits; Table lookup;
Conference_Titel :
Design Automation Conference, 1993, with EURO-VHDL '93. Proceedings EURO-DAC '93., European
Conference_Location :
Hamburg
Print_ISBN :
0-8186-4350-1
DOI :
10.1109/EURDAC.1993.410657
